IEEE Electrification Magazine - September 2017 - 66

Perturb
Postprocess

Perturb
Postprocess
Detect
Synthesize
Control

Perturb
Postprocess

Steady
State
Under
Start-Up Control

Perturb
Postprocess

vout(t)
iout(t)

Shutdown

t

TTOTAL
TIDENT

Parameter
Change

Success

Figure 19. An overview of the time schedule of the adaptive controller.

Lout

Lfilt

Rload
RC_ESR

+
Vg
-

Cfilt

+
ZCPL

Cout

Vout
-

Figure 20. A schematic diagram of the simulation test bed with a variable input filter, an output
bus capacitance, an output capacitor ESR, and a CPL.

34

Nominal
Increased Cout

33
32

30

28
0.25

Magnitude Gvd-Case 1 (After Fitting)

Estimation
Parametric Model
102

(a)

103

Phase of Gvd-Case 1 (After Fitting)

29

0.26

0.27

0.28 0.29
Time (s)

0.3

0.31

0.32

Figure 21. An output-voltage-reference step response for the nominal case (blue solid line) and for Case 1 before the control adaptation
(red dashed line).

66

50
40
30
20
10
0
-10
-20

31
Phase (°)

Output Voltage (V)

Magnitude (dB)

Nominal Converter Versus
Test Case 1-Before Control Adaptation

variations. For such a control scheme,
a possible timing schedule is as
depicted in Figure 19. The time duration TIDENT is the overall time required
for perturbing the system and postprocessing the collected data. A full
cycle of adaptation for the controller takes a time duration equal to
TTOTAL, which depends on TIDENT .
The controlled system performance is evaluated through a simulation test bed implemented in
MATLAB/Simulink. The converter
under study is a Buck converter shown
in Figure 20. Several tests are performed by varying the encircled
elements of the system. The performed tests include a change in the
output capacitance, insertion of an
undamped input filter representative
of the interaction with the source
subsystem, and change in a CPL, which
can represent reconfigurations occurring in a downstream regulated converter acting as a load subsystem.
For the sake of brevity, only the
results related to the first test case
(Case 1), i.e., the output capacitance
variation, are reported here. For an
increased output capacitor, the system response to an output-voltage
reference step change before control
adaptation is shown in Figure 21

I E E E E l e c t r i f i c ati o n M agaz ine / SEPTEMBER 2017

45
0
-45
-90
-135
-180
-225

Estimation
Parametric Model
102

Frequency (Hz)
(b)

103

Figure 22. The estimated control-to-output frequency response
Gvd(j~) for (a) the Case 1 off-nominal control-to-output transfer
function and (b) the fitted parametric model.



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