EDNE April 2012 - (Page 53)

designideas readerS SOLVe deSIGN PrOBLeMS Make an asynchronous clock for VPX-based PCIe systems Vadim Vaynerman, Bottom Line Technologies Inc, Westminster, MD DIs Inside 54 Use a photoelectric-FET optocoupler as a linear voltagecontrolled potentiometer 55 Wireless temperature monitor has data-logging capabilities 57 RC-timed shutoff function uses op amp and momentary switch ▶To see all of EDN’s Design Ideas, visit www.edn.com/designideas The VITA46 VPX standard defines a chassis that can accommodate all manner of cards with a common form factor (Reference 1). The cards plug into a common backplane. This design employs the VITA46.4 standard for PCIe to move data between peripheral cards and the host controller in a VPX system. It uses PCIe Revision 1, which runs at 2.5 Gbps. All VPXcompliant cards must use their own independent clocking, differing from other PCIe-compliant systems, such as PCs. VPX-peripheral cards must also ↘ create their own clock for PCIe transactions, meaning that the clock is not phase-coherent with the host singleboard computer. Thus, the peripheral clock is asynchronous. The PCIe standard allows for this situation and imposes a tight jitter tolerance on all asynchronous PCIe clocks. The peripheral card in this Design Idea uses an FPGA as the main digital-processing device. FPGA-vendor evaluation boards often feature PCIe interfaces but do not use asynchronous clocking on the board. To implement VCCO 3.3V asynchronous clocking, you use a clock chip that you carefully match to a particular model of oscillator crystal (Figure 1). The clock-chip IC has requirements C3 0.01 F PCIECLKS0 PCIECLKS1 PCIECLKSS0 C1 30 pF 1 2 X1 C2 30 pF 3 4 5 PCIEOE 6 7 PCIECLKSS1 8 C4 0.01 F VCCO 3.3V S0 S1 SS0 XIN VDDX 16 PCIE0P 15 PCIE0N 14 13 VCCO 3.3V R1 33 R2 33 R3 49.9 R5 33 R6 33 R7 49.9 R9 475 R8 49.9 R4 49.9 NORTHCLKP NORTHCLKN GNDO IC1 CY24293 12 XOUT VDDO PCIE1P 11 PCIE1N IREF 10 9 OE GNDX SS1 SOUTHCLKP SOUTHCLKN Figure 1 This circuit feeds a clock generator into an FPGA to make an asynchronous VPX clock. www.edn-europe.com APRIL 2012 | EDN EuropE 53 http://www.edn.com/designideas http://www.edn-europe.com

Table of Contents for the Digital Edition of EDNE April 2012

Cover
Contents
International Rectifier
Contents
RS Components
Masthead
Comment
International Rectifier
Pulse
Analog Devices
FTDI
Digikey
Mouser
Baker's best
Digikey
Test & Measurement
Agilent Technologies
Digikey
Protect POE systems
Hirose
Coilcraft
Mesago
Cover Story
Digikey
Signal Integrity
RS Components insert
Balancing GBWP and quiescent current
Noise wars
Design Idea
Product Roundup
Tales from the cube

EDNE April 2012