EDNE June 2012 - (Page 10)

pulse INNOVATIONS & INNOVATORS chronix Semiconductor has set a timescale for availability of its Speedster22i FPGA devices; the first, its HD series for communications routing and processing applications, will be shipped from the third quarter of 2012. Achronix, a fabless chip maker, has gained most attention for technology announcements of its HP family devices. HP FPGAs will use a pipelined, asynchronous-logic programmable logic core for the fastest possible throughput in applications such as intensive data-flow and DSP. The novel core will be surrounded by a “shell” of I/O that will nevertheless make the devices appear to the outside as a highperformance, but conventional, FPGA. Speedster22i HP chips will first become available in early 2013. The company’s HD series devices, the subject of the present announcement, by contrast are conventional FPGAs in the sense that they are SRAM-based, lookup-table (LUT)-architected chips. Their performance advantages – and Achronix claims “half the power and half the cost” of competing product lines – come largely from the fact that they are built on Intel’s 22-nm process. Intel terms one of the key features of the process “3-D Tri-Gate transistor technology” – otherwise known as fin-FETs. Intel is acting as a complete foundry for Achronix, including wafer fabrication, bumping and packaging. 22-nm finFETs enable a 50% reduction in power from the 28-nm process node, with a 37% increase in speed, matching the needs of high-end comms functions, Achronix says. Achronix is approaching one of the major problems for a recent entrant in FPGAS – namely, how do you compete in a market FPGAs gain speed and density from Intel process A so dominated by a very few established players? – by explicitly targeting specific markets. Speedster22i devices, it says, are the first FPGAs to include fully integrated hard IP protocol functions targeted for communications applications. The hard IP in Speedster22i devices includes the entire I/O protocol stack for 10/40/100 Gigabit Ethernet, Interlaken, PCI Express Gen 1/2/3 and memory controllers for 2.133 Gbps DDR3. In other FPGAs, Achronix asserts, these functions are implemented in the programmable fabric which consumes up to 500,000 equivalent look-uptables (LUTs), makes timing closure more challenging, and increases the cost and power. Embedded hard IP in Speedster22i FPGAs eliminates the cost of purchasing, integrating and testing these functions as soft IP. In particular, the company says, the demanding timing requirements of the DDR3 interface make it a bottleneck in many designs; you could avoid that problem using the hard-IP functions: similarly, the most timing-critical paths of a design will not be in the communications interface blocks, potentially shortening development times. The hard IP has been sourced from Intel and from one outside supplier, for a SERDES function. Applying its “edge” interfacing capabilities to the comms space, Achronix says that signals brought into a 200-G line card design would connect straight to the Speedster device and into its core for routing and packet management. The finFET provides a reduction in static power; for the communications interface functions, much greater reductions (a claimed factor of eight times) flow from the fact that they are not implemented in programmable fabric. There are 4 members in the HD family with the largest device having 1.7 million effective LUTs and 144 Mb of embedded RAM, plus up to sixteen 28-Gbps SERDES, sixty-four 12.75-Gbps SERDES and 960 general purpose 2.133-Gbps I/Os. The first part to be introduced will be the HD1000 with over 1 million effective LUTs and 84 Mb of embedded RAM. The chips will be packaged in conventional FbGA outlines, with a ball pitch of 1.0 mm. Achronix says it will offer 0.8-mm pitch packaging at some point, but that on devices with up to 2600 balls, maintaining a less-ambitious packaging format can help with the “escape” problem of routing PCbs, and with signal integrity. both the HD and HP families are designed with Achronix’s ACE design tools version 4.2 which are available now. The ACE design tools are built on the standard Eclipse Foundation open source platform and run under both Windows and Linux. Achronix provides HDL Synthesis tools from both Synopsys and Mentor Graphics as part of the ACE tool suite. —by Graham Prophet Achronix, www.achronix.com 10 EDN EUROPE | JUNE 2012 www.edn-europe.com http://www.achronix.com http://www.edn-europe.com

Table of Contents for the Digital Edition of EDNE June 2012

Cover
Agilent Technologies
Contents
International Rectifier
RS Components
Masthead
International Rectifier
Comment
Pulse
Analog Devices
Digi-Key
Farnell
NXP
Test & Measurement
Silicon Labs
Digi-Key
Test-driven development for embedded C: why debug?
Digi-Key
Baker’s best
Cover story
Rohde & Schwarz
Rohde & Schwarz
Rohde & Schwarz
Rohde & Schwarz
Rohde & Schwarz
Pico-projector design uses color LEDs
Digital isolation in smart energy metering applications
Mechatronics in design
Teardown
Design Idea
Product Roundup
Tales from the cube

EDNE June 2012

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