EDNE July 2012 - (Page 49)

designideas readerS SOLVe deSIGN PrOBLeMS Build a digital PLL with three ICs Dave Allen, Dash Inc, Kansas City, KS ↘ DIs Inside 51 Perform the XOR/XNOR function with a diode bridge and a transistor 52 Simple anticipator circuit improves on earlier idea ▶To see all of EDN’s Design Ideas, visit www.edn.com/designideas The simple circuit in this Design Idea exhibits the basic characteristics of a traditional analog phaselocked loop but has no analog components other than the reference oscillator. Other digital PLLs exist, including those employing an up/down counter, but this one is simpler and more flexible. The circuit initially found use more than 30 years ago as a clock regenerator in a data separator for a self-clocking code, such as Manchester or biphase, in magnetic recording. It quickly became clear that it has many other applications. The circuit also served as the basis of a servo controller for a tape drive’s capstan motor/tachometer. LSI disk/ tape-controller chips incorporated both the data separator and the capstan servo controller, with the advantage of having no analog circuitry and no requirements for adjustment. Because it was used in the production of commercially available products so long ago, it is not patentable today and is free for use. The example in Figure 1 uses only three ICs to make prototyping quick and the explanation simple. The connections between the 74161 counter outputs and the preset inputs form a rudimentary ROM implementing a look-up table (Table 1). The 16XREF should be a square wave or at least not a narrow pulse because you must take into account things that happen on both the leading and the trailing edges and setup times. The INPUT pulse must be long enough to meet the clock pulse-width requirements of the logic family you use for the 7474 D flip-flop. To test your prototype, make the INPUT approximately one-sixteenth of the 16XREF frequency and watch the output as you slowly vary the INPUT frequency. Use a signal generator that allows fine adjustment of the INPUT to measure lock range slightly above and below one-sixteenth of your XREF source. The dither is equal to the period of the 16XREF’s clock, but the output stays locked to the INPUT as you vary 5V the INPUT ±20% or more. You can temporarily disconnect Pin 9 of the counter to see the output slipping past the INPUT when the frequencies are close to each other. Reconnecting Pin 9 demonstrates the locking action. The output is a square wave when the INPUT is exactly one-sixteenth of 16XREF but becomes rectangular as you go above or below the center frequency. In operation, the counter counts continuously, but each rising edge of the INPUT signal causes a preset pulse at the counter. From Table 1’s count INPUT S1 VCC 5 2 D1 Q1 7474 3 6 C1 Q1 R1 7 1 4 14 11 2 12 D2 C2 10 S2 7474 R2 13 9 Q2 Q2 9 8 6 PE 16 VCC TC 15 OUTPUT 7404 1 16XREF D3 5 D2 4 D1 74161 3 D0 7 CEP 10 CET 2 CK GND 8 Q3 11 Q2 12 Q1 13 Q0 14 1 4 3 7404 R Figure 1 The counter loads its own data input to generate an output locked to the input signal. www.edn-europe.com JULY 2012 | EDN EuropE 49 http://www.edn.com/designideas http://www.edn-europe.com

Table of Contents for the Digital Edition of EDNE July 2012

Cover
Contents
International Rectifer
Microchip
FTDI
Masthead
Comment
International Rectifer
Pulse
Analog Devices
Digi-Key
Analog Devices
Test & Measurement
Agilent Technologies
Baker's Best
Messe München
Understand and characterize envelope-tracking power amplifiers
Digi-Key
Cover Story
Coilcraft
Digi-Key
Signal Integrity
Altera
USB 3.0 : Bringing SuperSpeed connectivity to mobile devices
Digi-Key
Developing high-frequency integrated circuits for test and measurement
Design idea
Product Roundup
Tales from the cube

EDNE July 2012