EDNE September 2012 - (Page 57)

must be verified against the original RTL. The absence of such verification can lead to nonfunctioning systems on chips or higher-than-desired leakage. Simulation approaches may be too slow, not cost-effective, and not exhaustive, leading to incomplete verification coverage of power optimizations. Traditional formal-equivalence tools typically target verification of combinational transformations and are inadequate for the kind of changes typically necessary for power optimizations. Most commercially available formalequivalence tools also suffer from capacity and performance limitations that must be overcome to handle low-power designs with complex power architectures and hundreds of power domains. A new class of formal-equivalence tools with high capacity and performance targeting verification of sequential transformations must evolve to meet these new requirements. According to Lauro Rizzatti, general manager of Eve-USA, power optimization also presents challenges for EDA vendors. Many low-power techniques are generally incongruent with RTL simulation or emulation, which abstracts out any notion of voltage. Designers must adapt these digital tools to support power intent and low-power-optimization techniques for implementation. Power-deliVery Networks According to Dermott Lynch, vice president of marketing at Silicon Frontline Technology, power devices typically operate at 70 to 90% efficiency, which results in a loss of 10 to 30% of overall system power. Ely Tsern, vice president and chief technology officer for Rambus’ semiconductorbusiness group, adds that more aggressive power-mode transitions, with finer-grained power domains, will result in faster transition of local supply currents, which in turn can induce greater di/dt supply noise for sensitive local circuits, especially analog circuits. Shanmugavel cautions, however, that, under all conditions, the power-delivery network should be able to sustain the load without compromising the voltage integrity. For example, when a global clock transitions and a functional unit turns on to perform a task, a transient-current demand occurs. This transient current can be three to five times that of the nominal current, depending on the functional block, which places an enormous load on the power-delivery network. You must validate the transient voltage noise on the network under these circumstances.EDN refereNce Chandrakasan, Anantha P; and Robert W Brodersen, “Minimizing Power Consumption in CMOS Circuits,” University of California—Berkeley, http://bit.ly/HIetoD. 1 you can reach contributing technical editor Brian Bailey at brian_bailey@acm.org. www.edn-europe.com sEPtEmbER 2012 | edn eUrope 57 http://digikey.com/europe.com http://www.bit.ly/HIetoD http://www.edn-europe.com

Table of Contents for the Digital Edition of EDNE September 2012

Cover
Contents
International Rectifier
Microchip
RS Components
Masthead
Microchip
EDN Comment
Pulse
Analog Devices
Altera
Baker's best
Messe München
Test & Measurement World
Agilent Techno
Digi-key
Bergquist
Advanced power switches boost microhybrid emissions gains
Digi-Key
Image sensors evolve to address Emerging embedded- vision needs
Renesas
Silicon Labs
Digi-Key
Vicor
Power becomes a software issue as smart phones become smarter
IAN
Power : a significant challenge in EDA design
Digi-Key
Mechatronics in Desin
Design Ideas
Product roundup
Tales from the Cube

EDNE September 2012