Aerospace & Defense Technology - December 2022 - 21

RF & Microwave Technology
problem and easily implemented in
copper, becomes more challenging in
the shift to a fiber transport layer.
An experimental fiber-based prototype
has been designed to evaluate its suitability
as an alternative to copper as well as
to identify any performance effects introduced
by temperature and other environmental
factors.1
In the initial experimental
phase, the physical fiber link is a
modest ten meters - enabling significant
separation between the microwave RF
analog and data processing domains.
ODH Implementation
The main challenges defined at the
start of this project were twofold:
1. Ensuring the reliable transport of relatively
slow control signals of which
the most important is;
2. The delivery of error-free, deterministic
synchronization to multiple converters
to ensure system-level determinism
and thus synchronous
sampling. This remains on the work
in progress list at this point.
Earlier efforts working with fiber links
have been described in a combined control
and data context. One of note, from
Lincoln University in the UK, describes
an FPGA-based project2
to aggregate SPI
and GPIO data, to be sent over a single
optical link. The article describes data
coding approaches for extended transmission
distances and illuminated the
challenges arising. The earlier conclusions
were:
* Care to establish reliable link synchronization,
necessitating a master reference
clock.
* Encoding is a key success factor. In the
example described, 8b/10b coding
proved orders of magnitude better than
other simpler coding schemes (such as
exclusive OR - XOR, or Grey codes).
* Finally, if latency is important, as it is
for this experimental work, the
authors detailed how re-synchronizing
the link could compensate for
known system latencies.
This previous work forms a basis
from which to extend the current prototype
work. A new solution proposed
(Figure 1) takes economic, low-power
programmable logic devices (here
FPGAs) to be configured as simple coding
engines with the objective to format,
aggregate and serialize slow control
vectors generated directly from
system GPIO and SPI messages. Encoded
message vectors are then transported
across three parallel optical lanes
with a reference clock and a discrete
coded SYNC signal.
Experimental Implementation
The starting point for the prototype
is an existing high-end IC evaluation
system. A system comprising an
advanced microwave front end card for
the EV12AQ600 was selected. This
quad channel, 12-bit 6.4 Gsps broadband
RF ADC with the ability to sample
up to 6.4 GHz offers a suitable FMC
based target ADC for the prototype
work. The EV12AQ600 has been
designed to mount directly onto a powerful
signal processing (DSP) card using
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Aerospace & Defense Technology - December 2022

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