Lasers & Optics CAD model of the VS20 Core is shown in Figure 2(e). The image sensor and internal TEC and thermistor are housed inside a 28-pin hermetically sealed metallic sensor package with a double-side anti-reflection (AR) coated Sapphire glass window providing >90 percent transmission over the wavelength range 400 to 2,500 nm. A custom-designed ceramic interposer provides routings from the IO ring pads on the sensor to the output pins on the package. The ADCs on the sensor front-end board digitize the VGA sensor's differential output signal as well as the voltage over thermistor for TEC control. The TEC controller is bi-directional so that the sensor can be cooled and heated. The main component of the processing board is the SoC processor comprised of a dual-core Cortex-A53 and a dual-core Cortex-R5 real-time processing unit mated with programmable logic. DDR memory is used as a frame buffer for the image frames read from the sensor. Real-time image processing takes place in the ARM processor/FPGA depending on the set frame rate. Under typical use-case conditions, the camera power consumption remains below 12 W for operation up to 400 fps. Fabrication, Assembly and Measurement The Emberion in-house designed imager circuit is taped-out and manufactured at a semiconductor foundry. The CMOS wafers are then planarized using a sequence of post-process steps to achieve a surface profile optimal for the latter CQD stack process steps. The absorber stack is processed in-house using Emberion's custom-built pilot manufacturing line including wet-deposition, sputtering, evaporation, and ALD process steps. The image sensors are measured at waferlevel before die selection and packaging assembly. Finally, the packaged imager is assembled into the camera for camera testing and measurement. Wafer Post-Process The image sensor ROICs are fabricated on 200 mm wafers using a standard 180 nm node CMOS foundry process. The as-received CMOS wafers require planarization so that deposition of uniform and high-quality thin-film photodiode layers is possible. The Damascene planarization process is used here to achieve maximum step heights below 50 nm across the pixel array and exhibiting at most 200 nm dishing at the IO pad ring and saw lane regions. Pixel electrodes with below 50 nm thickness are sputter-deposited and lithographically patterned onto the planarized wafer surface. Figure 3(a) shows the visual appearance of the wafer after planarization and metallization steps. The typical features of the pixel electrodes and vias prior to stack processing are displayed in Figure 3(b-c). Aerospace & Defense Technology, June 2024 TB Sealevel Systems Ad 0324.indd 1 mobilityengineeringtech.com 2/14/24 10:45 AM 17http://info.hotims.com/86256-742 http://mobilityengineeringtech.com