Tech Briefs Magazine - September 2024 - PIT-5

Fixed Input signal
Input Signal Sweep (For Linearity Plot)
Reference
Generator
Dark
ADC
section
ADC
section
ADC
section
ADC
section
ADC
section
ADC
section
ADC
section
ADC
section
ADC
section
Reference Routing Resistance
Supply/Ground Routing Resistance
Figure 6: INL Simulation testbench. In this diagram, the ADC array is divided into nine sections. (Image: Forza Silicon)
The nonlinearity becomes more significant
for faster ADC count rates,
which are used to reduce effective row
time to achieve high frame rate. To reduce
the disturbance, there are multiple
options. First, the drive strength of
the bias generator can be increased to
decrease the impedance of the bias
node, which will help in a faster settling
of the disturbance. Second, the number
of fast switching gates on the same power
domain can be decreased, which aids
in the reduction of the IR drop on the
supply/ground. This is accomplished
by moving these devices to a different
power domain. Careful consideration
should also be given to minimizing supply/ground
routing resistance.
Another approach is to reduce the effect
of the glitch on the victim ADCs.
This can be achieved by sampling the
bias voltage in each ADC separately. As
a result, the disturbance will not propagate
through the bias net; any disturbance
on the supply/ground will be
mirrored on the sampled bias voltage,
maintaining the same VGS. Proper care
should be taken to size the sampling
cap so the supply/ground disturbance
does not change the VGS. A trade-off of
sampling the comparator bias voltage is
the introduction of kTC noise. Since
the comparator follows the preamplifier
in the signal chain, the effect of kTC
on the input-referred ADC temporal
noise is usually insignificant.
To investigate this effect, the ADC
array is modeled and INL plotted.
Routing resistance for all the supplies,
grounds, biases and ramp is modeled
in the simulation testbench. The references
- ramp and biases - are routed
horizontally. Supplies and grounds are
routed horizontally and vertically. The
ADC array is modeled by dividing it
into sections and using m-factor. Special
care is taken in deciding on the
number of sections needed to model
the array so that any supply/ground-rePhotonics
& Imaging Technology, September 2024
0.2
0.4
0.6
−1.4
−1.2
−1.0
−0.8
−0.6
−0.4
−0.2
INL Comparison
Original
200
Modified without comparator bias sample
400
Figure 7: INL plot comparison. (Image: Forza Silicon)
lated variation can be simulated in a
reasonable runtime. Dark columns are
also included in the testbench. The
ADCs are RC extracted so the effect of
parasitic capacitance can be seen in
the results. Vertical routing for the
supplies and ground is carefully modeled
to represent actual routing in the
sensor. The testbench is set up so that a
section of the array is kept at a fixed
dark signal level. The input to the remainder
of the ADCs in the array is
swept to their INL plot. Linearity of
each section is compared to determine
if there is any spatial pattern. The
block diagram of the testbench is
shown in Figure 6.
The simulation result before and after
modifications is shown in Figure 7.
The INL plot is for the first 25 percent
of the signal range. The original result
displays the INL plot, with no modifications.
The next two plots show the INL
with the modifications mentioned in
the previous section. In one plot the
comparator bias is not sampled, while
in the other case the comparator bias is
sampled. As can be seen, the INL improves
significantly when the comparator
bias is sampled.
This article has presented an analysis
and simulation methodology for predicting
the low-light nonlinearity in an
ADC array. Conventional sources of
INL are well understood, but as pixel
array resolution has increased and
ADC pitch has consequently been reduced,
additional array sources of nonlinearity
have become prominent. Multiple
possible sources can affect the
common nets in an ADC array, most
prominently ramp and biases. Methods
to reduce this disturbance are presented,
which require some careful design
choices. A method to identify the
sources is also presented, which requires
careful modeling of the ADC
array. Simulated results reveal a dip in
INL at low code levels that improves
following modifications.
This article was written by Jatin Hansrani,
Senior Analog Design Engineer,
Forza Silicon Corporation (Pasadena,
CA). For more information visit www.
forzasilicon.com.
5
600
Output Code, DN
Modified with comparator bias sample
800
1000
INL, DN
http://www.forzasilicon.com

Tech Briefs Magazine - September 2024

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Tech Briefs Magazine - September 2024 - Intro
Tech Briefs Magazine - September 2024 - Sponsor
Tech Briefs Magazine - September 2024 - Cov1
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