IEEE Solid-State Circuits Magazine - Winter 2018 - 9

of an N-type MOS (NMOS) and a
P-type MOS (PMOS) transistor. When
the input voltage is stepped down
suddenly to 0 V, the NMOS transistor turns off, and the PMOS transistor provides a current to the output
node so as to "pull up" the output
node to the power supply, VDD. This
current is not constant; it varies as
the output node voltage begins to
rise toward VDD, and it depends on
the PMOS characteristics. However,
in addition to this current, due to
thermal noise, there is a noisy current, albeit small, that contributes
to this charging up process. This
is modeled as I n2 (t) in Figure 2(b).
As a result, t pd may become slightly
smaller or larger than the nominal
t pd, depending on noise values in
this process. Similarly, due to the
noise of the NMOS transistor [I n1 (t)
in Figure 2(c)] during the pull down,
t pd deviates from its nominal t pd.
The waveforms corresponding with
the rising input voltage is shown
in Figure 3.
Let us call the random deviation
from the nominal t pd "excess delay,"
as shown in Figure 3. Since each
period of the clock corresponds to
6t pds, there will be six excess delays
that add up dur ing each per iod.
We denote these six excess delays
by X 1 [n] to X 6 [n], where n denotes
the cycle number. For example, X 1 [1],
X 1 [2], and X 1 [3] refer to the excess
delays of the first inverter in the ring
immediately following the first, second, and third rising edges of the
clock (i.e., the rising edges of v 3 ),
respectively. Similarly, X 4 [1], X 4 [2],
and X 4 [3] refer to the excess delays
of the first inverter in three consecutive cycles, but immediately following three falling edges of the clock.
The excess delays are indeed random, as their underlying noise is
totally unpredictable, and they are
functions of time. This makes the
excess delay a random process or a
random signal. Since we are only
interested in the deviations from the
nominal time, not in the nominal time
itself, we only need to keep track of
all the excess delays as we go through
the ring. This is shown in a model in

Figure 4, where an inverter is modeled
as a summer, adding the accumulated
excess delays from the past to the
excess delay being produced at present. If we denote the random deviation at the nth period of oscillation as
Yn,then we can write

tpd
0
t

In a sense, we keep adding the
outcomes of random variables as
the time progresses. However, given
that X 1 to X 6 are essentially the
same random variables, having the
same probability density functions,
only tried at different time instants,
Yn can be thought of as the sum of
outcomes of repeated trials of one
random variable. This process is
known as a random walk process in
the literature [1], and we will explain
it briefly here.

Excess Delay

Figure 3: The CMOS inverter input and
output corresponding to Figure 2(c). Due to
the thermal noise of the NMOS transistor,
there is an excess delay between the input
and output.

backward) is totally independent
of other steps. This is referred to
as independent and identically distributed (i.i.d) random variable. The
resulting distance from origin as a
function of N (or time in general) is
referred to as a random walk process. After N trials, it is possible for
you to move N steps forward, with a
probability of ^1/2hN . Also, with the
same probability, you may end up N
steps backward. But it is more likely
that you will end up somewhere in
between. What is interesting about
this process is that your expected
distance from origin after N steps is
actually zero (i.e., as if you have not
moved at all), but the spread of possibilities will become larger as you

Random Walk Process
Consider standing at point 0 facing north and letting a flip of a fair
coin decide whether to move one
step forward or backward. If the
flip results in heads, you move one
step forward. If tails, you move one
step backward. You then repeat this
experiment for N trials, taking a
total of N steps (some forward, some
backward). Note that every step follows the same type of randomness
(a flip of the same coin), yet every
step outcome (being for ward or

X6[n -1]

X1[n]

2

X2[n]

vo(t)

VDD/2

Yn = Yn - 1 + X 1 6n@ + X 2 6n@ + X 2 6n@
+ X 4 6n@ + X 5 6n@ + X 6 6n@ .

1

vin(t )

VDD

X3[n]

3

X4[n]

X5[n]

X6[n]

Y [n -1]
Cycle n -1

X1[n +1]

Y [n ]
Cycle n

Cycle n +1

Figure 4: Excess delays of the present cycle are added to the accumulated excess delays from
previous cycles (Y[n-1]) to produce the total excess delay at the end of the current cycle (Y[n]).

IEEE SOLID-STATE CIRCUITS MAGAZINE

W i n t e r 2 0 18

9



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2018

Contents
IEEE Solid-State Circuits Magazine - Winter 2018 - Cover1
IEEE Solid-State Circuits Magazine - Winter 2018 - Cover2
IEEE Solid-State Circuits Magazine - Winter 2018 - Contents
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