Potentials - January/February 2016 - 33

is presented herein as a strategy
for enabling a single low-cost platform based on a field-programmable gate array (FPGA) that can be
used in a large repertory of video
processing applications. The platform is designed to real-time highpixel-rate applications, since the
data throughput is a reconfigurable parameter and can assume
values very significant when compared to those provided by current
scientific literature.
This article reports on the development of an important part of the
stream-based JPEG-LS video compression system, the input interface.
The input interface is in charge of
receiving the serial video source and
distributing it to multiple PUs, each
of them implementing the LOCO-I
algorithm. Other required features
of the input interface are low power
consumption and reduced logic circuitry, so as to not constitute a bottleneck for the whole video processing system, which should allow the
PUs the largest processing capacity.
Furthermore, we verify the achieved
data throughput (maximum pixel
rates) with a different number of
PUs, emphasizing the potentialities
of spatial parallelism at reconfigurable architectures for meeting requirements of performance.
The input interface is composed
of parameterized and reconfigurable
structures, which are implemented
in FPGA. The development was performed within Quartus II, an environment dedicated to synthetizing
digital systems and designed by Altera. The platform used for the validation tests was the DE2-70, manufactured by Terasic Technologies,
based on the Altera Cyclone II FPGA
EP2C70896C6.

Table 1. The influence of the use of SIMD machines

in compression ratio.
Image

N=1

N=2

N=4

Delta (N = 2)

Delta (N = 4)

Barbara
Peppers

1.6833
1.8443

1.6998
1.8451

1.7056
1.7494

0.0165
0.0008

-0.0949

Lena
Sailboat

1.8656
1.6622

1.8692
1.6601

1.8719
1.6651

-0.0021

0.0063
0.0028

Goldhill

1.6847

1.6857

1.6819

0.0010

-0.0029

Cameraman

1.6446

1.6743

1.8166

0.0297

0.1720

Regarding specifically the current literature on JPEG-LS compression, several works, despite achieving high pixel rates, explore neither
spatial parallelism (SIMD machines)
nor configurability to meet different
demands for frame acquisition rate
and image spatial resolution. Table 2
summarizes some related works
in terms of their maximum data
throughput, also comprising their
implementat ion cha racter ist ics
such as parallelism, scalability, and
FPGA application. In (Li et al. 2007),
for example, the implementation of
JPEG-LS in a parallelism-based architecture with power consumption
management reach 10 MP/s while,
in (Fang et al. 2003), it met the processing rate for 30 frames of 1280 #
720 pixels/s or, similarly, 27.65 MP/s.

the proposed input interface
for the JPEG-ls parallel
reconfigurable architecture
In the parallel hardware architecture proposed within this work, the
pixels of the video data stream are
not stored in external memory; they
are stacked in sequence by the
input interface and then distributed

to the corresponding PUs, which are
mapped into vertical partitions of
the image, as depicted in Fig. 1.
Each PU is accomplished with the
LOCO-I compression algorithm.
The LOCO-I is built upon a prediction mask, as presented in Fig. 1,
composed of five pixels: the current
pixel X (the one being processed)
and four other pixels that spatially
surround X. These pixels, called
context-pixels, are simultaneously
necessary for encoding X. To reduce
the number of memory accesses, the
input interface provides the corresponding PUs with the five pixels in
the parallel format.
The context pixels belong to either the current line (Ra and X)
or to the previous video line (Rb,
Rc, and Rd). Thus, two video lines
should be previously stored by the
input interface to enable spatial
parallelism, which stems from simultaneous and synchronized operation of the PUs while a single
video data stream feeds the input
interface. The storage of the current
video line being received is necessary for the clock domain change,
allowing each PU to operate at

Table 2. The proposed architecture in comparison

with other works on JPeG-lS implementation.

Existing work in the area
Although there are studies exploiting data parallelism in general
image and video processing systems, they are dedicated primarily
to the design of the processing unit
(Wang et al. 2010), (Yu et al. 2008),
(Klimesh et al. 2001), giving little or
no emphasis on the design of the
input interface.

0.0036

0.0223

Klimesh et al. 2001
Fang et al. 2003
Li et al. 2007
Yu et al. 2008
Wang et al. 2010
Proposed

max Data
throughput
(mpIxels/s)

sImD
machINe

scalable
throughput

Fpga
ImplemeNteD

1.33
27.65
10
48
75
196.9

No
No
No
No
No
Yes

No
No
Yes
Yes
No
Yes

Yes
No
Yes
Yes
Yes
Yes

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