IEEE Power Electronics Magazine - June 2022 - 82

Expert View
by Dinesh Ramanathan
Avalanche and Short Circuit
Robustness of Vertical GaN FET
G
aN power semiconductor
devices have been the
recent focus of intense
development efforts due to the
promising material properties of
GaN for next-generation power
electronics applications. For power
switching and rectifying applications,
the ruggedness in breakdown
is a critical requirement as
addition of snubber circuits
reduce the performance and efficiency
of the system. Lateral GaN
high-electron mobility transistors
(HEMTs) have been commercialized
up to 900 V class recently, but
they lack avalanche capabilities.
Vertical GaN transistors demonstrate
several advantages over lateral
GaN HEMT: 1) higher breakdown
voltage (BV) and current for a
given chip area, 2) higher reliability,
3) easier thermal management,
4) avalanche capabilities, and 5)
short-circuit robustness.
Among the var ious possible
approaches to GaN based power
electronics systems, vertical devices
on GaN substrates offer the advantage
of better area efficiency due to
the ability to grow thick drift regions
and improved reliability due to the
reduced defect density. The devices
demonstrate a non-destructive BV
with positive temperature coefficient
robust avalanche under the
Digital Object Identifier 10.1109/MPEL.2022.3171717
Date of current version: 16 June 2022
unclamped inductive switching conditions.
Double pulse tests reveal
significantly less than ~10 ns switching
times and small
turn-on/off
switching losses. The body diode
shows almost no reverse recovery.
These results present a significant
performance advancement in vertical
GaN transistors.
An avalanche event in a semiconductor
is a form of electric current
multiplication that can allow very
large currents within materials
which are otherwise good insulators.
When a power semiconductor device
exceeds the breakdown voltage, the
resulting electric field becomes
strong enough to create additional
carriers. In this case, free carriers
collide with and dislodge carriers
from the lattice. These newly dislodged
carriers create new additional
free carriers and an immediate
increase in free carriers, resulting
in avalanche breakdown. In other
GaN technologies, like the GaN-onSi
HEMT,
the leakage gradual ly
increases through sub-surface conduction
and, thus, avalanche behavior
is not realized. This results in
power system engineers having to
put expensive clamping circuits to
ensure the power semiconductor
behaves appropriately under unexpected
voltage fluctuations.
Unlike GaN-on-Si, the NexGen
Vertical GaN (Figure 1) has a P-N
junction and this enables the device
to show both single and repeated
82 IEEE POWER ELECTRONICS MAGAZINE z June 2022
cycle avalanche robustness. It allows
reverse biased voltage to exceed the
maximum breakdown voltage value
for a specified energy and current
limitations. This means that when
faced with a situation where the system
voltage exceeds the breakdown
voltage of the device, the vertical
GaN power semiconductor avalanche
circuits don't require external voltage
clamping c omponents. In-house tests
have shown that the 1200 V rated Vertical
GaN device can consistently
avalanche at 1400 V1 [Figure 2(a)].
In typical power electronic systems,
number of overload operational
conditions must be considered to
ensure the device and system/circuit
robustness. Typically, these conditions
are managed by system-level
failure-detection and shut-down
mechanisms to avoid destructions.
Therefore, a crucial device withstand
capability is required, to guarantee
their intervention. A short circuit
(SC) event can occur in a variety of
ways in an industrial or automotive
environment. This is especially true
for all power electronic systems,
where different kinds of protection
circuits were proposed to avoid catastrophic
failure during overload and
SC events in the power stage. Therefore,
in this scenario a device should
be designed to have reasonable SC
withstand time prior to the intervention
of the protection circuitry. Nevertheless,
this could not be achieved
without an understanding of the
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