IEEE Spectrum November, 2011 - 63

Transistor Wars
Continued from page 53

carry about 25 percent more current than a UTB SOI. This current boost doesn't matter much if you have only a single transistor, but in an IC, it means you can charge capacitors 25 percent
faster, making for much speedier chips. Faster chips obviously mean a lot to a microprocessor manufacturer like Intel.
The question is whether other chipmakers will find the faster
speeds meaningful enough to switch to FinFETs, a prospect that
requires a big up-front investment and an entirely new set of
manufacturing challenges.

he single biggest hurdle in making FinFETs is
manufacturing the fins so that they're both narrow and
uniform. For a 20-nm transistor-roughly the same
size as the one that Intel is putting into production in
2012-the fin must be about 10 nm wide and 25 nm high;
it must also deviate by no more than half a nanometer-just a
few atomic layers-in any given direction. Over the course of
production, manufacturers must control all sources of variation,
limiting it to no more than 1 nm in a 300-millimeter-wide wafer.
This precision is needed not only to manufacture the fin;
it must also be maintained for the rest of the manufacturing
process, including thermal treatment, doping, and the multiple film deposition and removal steps needed to build the
transistor's gate insulator and gate. As an added complication,
the gate oxide and the gate must be deposited so that they follow the contours of the fin. Any process that damages the fin
could affect how the device performs. The resultant variation
in device quality would force engineers to operate circuits at a
higher power than they're designed for, eliminating any gains
in power efficiency.
The unusual geometry of the FinFET also poses challenges
for doping, which isn't required but can help cut down on
leakage current. FinFET channels need two kinds of dopants:
One is deposited underneath the gate and the other into the
parts of the channel that extend on either side of the gate, helping mate the channel to the source and drain. Manufacturers
currently dope channels by shooting ions straight down into
the material. But that approach won't work for FinFETs. The
devices need dopants to be distributed evenly through the top
of the fin and the side walls; any unevenness in concentration
will cause a pileup of charges, boosting the device's resistance
and wasting power.
Doping will get only more difficult in the future. As
FinFETs shrink, they'll get so close together that they will
cast "shadows" on one another, preventing dopants from permeating every part of every fin. At Applied Materials' Silicon
Systems Group, we've been working on one possible fix:
immersing fins in plasma so that dopants can migrate directly
into the material, no matter what its shape is.
Because UTB SOI devices are quite similar to conventional
planar CMOS transistors, they are easier to manufacture than
FinFETs. Most existing designs and manufacturing techniques will work just as well with the new thin-silicon transistors as they do with the traditional variety. And in some
ways, UTB SOIs are easier to produce than present-day transistors. The devices don't need doped channels, a simplification
that can save planar CMOS manufacturers some 20 to 30 steps
out of roughly 400 in the wafer production process.
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Table of Contents for the Digital Edition of IEEE Spectrum November, 2011