IEEE Spectrum November, 2013 - 28

NANOMETERS
what's in a naMe? Key chip dimensions,
such as the transistor gate length [yellow] and
the metal half pitch [orange]-half the distance
spanned by the width of a wire and the space
to the next one on the densest metal layer of
a chip-have decreased but not strictly tracked
the node name [red]. These numbers, provided
by GlobalFoundries, reflect the company's plans
to accelerate the introduction of 14 nm chips in
2014, a good year early.

100

0
2007

2009

Technology Roadmap for Semiconductors, says the node is and
always has been defined by the proximity of wires on the first metal
layer on the back of the chip, a dimension that was reflected well in
DRAM and, later, flash memory, but not in logic.
rEgardlEss Of dEfiniTiOn, numbErs in nOdE namEs havE

continued to decline. Along with them, the distance between
transistor gates and that between the closest copper wires on the
back of the chip have also decreased. Both of those features help
define how dense a chip can be and thus how many more you can
produce on a single silicon wafer to drive down costs.
But the difficulty inherent in printing ever-finer features has
now taken its toll. "When we got to around 28 nm, we were actually pushing the limits of the lithographic tools," says Subramani
Kengeri, vice president of advanced technology architecture at
GlobalFoundries, the world's second-biggest chipmaking foundry
after Taiwan Semiconductor Manufacturing Co.
To deal with this, Kengeri and his colleagues were forced to adopt
a lithographic technique called double patterning. It lets technicians pattern smaller features by splitting a single patterning step
into two, relying on a slight offset between the two steps.
Intel used the technique to form transistors on its 22-nm chips, but
it stuck to single patterning to make the densest metal layer. Pushing
the technique to its limits, the company made wires with a pitch of
80 nm, which encompasses the width of one wire and the space to

2011

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the next. By adopting double patterning, GlobalFoundries and others
could push the pitch down to about 64 nm for their 20-nm chips.
But that move came with a significant trade-off: Double-patterned
chips take longer to make, adding significantly to the cost.
Carrying this technique over from the 20-nm node to 14 nm
would mean that chipmakers would have to double-pattern even
more layers of the chip. So last year, Kengeri and his colleagues
announced a chip industry first: They would put a stop to the
shrink. GlobalFoundries' line of 14-nm chips, which are slated to
begin production in 2014, may be the foundry world's first FinFET
transistors. But the company will build the new chips with the
same wiring density used in its 20-nm chips. "The first-generation
FinFET is basically reusing all of that and plugging a FinFET into
that framework," Kengeri says. "It's really a 20-nm FinFET, in a way."
Nevertheless, the company refers to these as 14-nm chips because
they offer roughly a generation's-worth jump in performance and
energy efficiency over its 20-nm chips.
Kengeri hopes that by putting a one-generation pause on shrinking
chips and focusing on introducing 3-D transistors, GlobalFoundries
will catch up with Intel, which is already shipping 3-D devices in its
22-nm chips. GlobalFoundries' 14-nm chips aren't any denser than-
and therefore cost just about as much as-the previous generation,
but they're still a big improvement, Kengeri says. "Our point-and our
customers agree-is that as long as they see that value, they don't
care what the technology is called or what is inside."

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Data Source: globalfounDrieS

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Table of Contents for the Digital Edition of IEEE Spectrum November, 2013