IEEE Circuits and Systems Magazine - Q2 2021 - 115

as well. Furthermore, such a system would require additional
guarantees on the absence of deadlock and appropriate
buffering to accommodate the desired number
of tokens on each dataflow path. Enabling dataflow
kernel replication as well as multithreaded execution
on a single kernel has the potential to significantly
improve parallelism and resource utilization, hence
bringing a completely new optimization dimension to
dataflow design.
C. Reconfigurable Dataflow Architectures
So far, we have only attempted to map our dataflow circuits
to standard FPGAs-a natural alternative to explore
are coarser reconfigurable arrays, whose limited
flexibility as well as word-oriented nature promise efficiency
in area, timing, and energy [35]. The absence
of a centralized controller and the systematic pairing
of data with handshake signals makes dataflow circuits
particularly well-suited for such architectures: each array
tile would be composed out of one or more dataflow
primitives and the interconnect between tiles would
carry data bundled with its control signals, as suggested
in Figure 18.
One of the major challenges is to design an array that
is structurally adequate for the computational patterns
and interconnects which typically appear in dataflow
circuits. Intuitively, circuits obtained from high-level
code share some representative properties (e.g., BB organization
with merges and branches at the inputs and
outputs, respectively) which can be exploited to customize
the array tiles. Our existing compilation flow can be
used to translate a program into a functional netlist of
hardware primitives; we would need to develop custom
place-and-route techniques which exploit array-specific
transformations and optimizations to map these netlists
onto the underlying architecture and to enable efficient
architectural exploration.
X. Related Work
In this section, we outline what others have done to circumvent
some of the problems of statically scheduled
HLS and we contrast our work with other dataflow-oriented
approaches.
A. Towards Dynamic Scheduling
Recent advances in HLS have explored methods to
overcome the conservatism in static scheduling and
to remove the inability of HLS tools to handle dynamic
events. Several techniques [1, 47] generate multiple
schedules which are dynamically selected during runtime,
once the values of all parameters are known;
they rely on the capabilities of current HLS tools by
replicating the source code and dynamically selectSECOND
QUARTER 2021
ing which copy of the code needs to be executed.
The drawback of these approaches is that they apply
to only some very particular cases of dependences
through memory; they are also affected by the area
(or reconfiguration) overhead of synthesizing two
or more versions of an accelerator and the cost of
switching between them.
Tan et al. [63] describe an approach called ElasticFlow
to apply loop pipelining on a particular class of irregular
loop nests with no inter-iteration dependences
in the outer loops. In their approach, multiple pipeline
instances of a dynamic-bound inner loop are scheduled
to execute in parallel. Dai et al. [20] propose methods
for pipeline flushing by performing static scheduling for
multiple initiation intervals of the pipeline to resolve different
possible resource collisions; they later developed
application-specific dynamic hazard detection circuitry
[21] and have shown the ability of speculation but with
stringent constraints (i.e., the approach lacks generality
in the ability to revert arbitrarily the state after failed
predictions). Nurvitadhi et al. [53] perform automatic
pipelining, assuming that the datapath is already partitioned
into pipeline stages. The underlying methodology
in all these techniques is still based on static scheduling
adapted to enable some level of dynamic behavior,
which limits the achievable performance improvements
only to some particular cases. We think that this body
of recent work points to the importance of the ultimate
Tile of Dataflow
Primitives
Reconfigurable
Interconnect
Figure 18. A reconfigurable dataflow array, with tiles composed
out of fixed interconnects of dataflow primitives. All
connections carry data bundled with its control signals.
IEEE CIRCUITS AND SYSTEMS MAGAZINE 115
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