IEEE Circuits and Systems Magazine - Q2 2021 - 20

350 nm 150 nm 130 nm 90 nm
28 nm
14 nm
100
120
140
20
40
60
80
1,000
10 k
100 k1 M
Number of LEs (4-LUT Equivalent)
Figure 14. Trends in memory bits per LE for Altera/Intel FPGAs starting from the
350 nm Flex 10k (1995) to the 10 nm Agilex (2019) architecture. The labels show the
sizes of BRAMs in each of these architectures.
simplify both the FPGA layout as well as RAM mapping
and placement. Tatsumura et al. [52] plot a similar trend
for on-chip memory density in Xilinx devices as well. Similarly
to Intel, Xilinx's RAM architecture combines LUTRAM
and a medium-sized 18 kb RAM, but also includes
hard circuitry to combine two BRAMs into a single 36 kb
block. However, Xilinx's most recent devices have also
included a large 288 kb BRAM (UltraRAM) to be more efficient
for very large buffers, showing that there is still no
general agreement on the best BRAM architecture.
To give some insight into the relative areas and efficiencies
of different RAM blocks, Table II shows the resource
usage, silicon area, and frequency of a 2048 × 72-bit
logical RAM when it is implemented by Quartus (the
CAD flow for Altera/Intel FPGAs) in a variety of ways on
a Stratix IV device. The silicon areas are computed using
the published Stratix III block areas from [63] and scaling
them from 65 nm down to 40 nm, as Stratix III and IV have
the same architecture but use different process nodes.
As this logical RAM is a perfect fit to the 144 kb BRAM in
512 b/4 kb/512 kb
2 kb
9 kb/144 kb
10 nm
20 kb
65 nm
40 nm
Stratix IV, it achieves the best area
when mapped to a single 144 kb
BRAM. Interestingly, mapping to
eighteen 9 kb BRAMs is only
19 . #
larger in silicon area (note that
output width limitations lead to 18
BRAMs instead of the 16 one might
expect). The 9 kb BRAM implementation
is actually faster than
the 144 kb BRAM implementation,
as the smaller BRAMs have higher
maximum operating frequencies.
Mapping such a large logical RAM
to LUT-RAMs is inefficient, requiring
12
.7# more area and running at
40% of the frequency. Finally, mapping
only to the logic and routing
resources shows how important
on-chip RAM is: area is over 300#
larger than the 144 kb BRAM. While
the 144 kb BRAM is most efficient
for this single test case, real designs have diverse logical
RAMs, and for small or shallow memories the 9 kb and
LUT-RAM options would outperform the 144 kb BRAM,
motivating a diversity of on-chip RAM resources. To
choose the best mix of BRAM sizes and maximum word
widths, one needs both a RAM mapping tool and tools to
estimate the area, speed and power of each BRAM [55].
Published studies into BRAM architecture trade-offs for
FPGAs include [30], [55], [64].
Until now, all commercial FPGAs use only SRAM-based
memory cells in their BRAMs. With the desire for more
dense BRAMs that would enable more memory-rich
FPGAs and SRAM scaling becoming increasingly difficult
due to process variation, a few academic studies (e.g. [52],
[65]) have explored the use of other emerging memory
technologies such as magnetic tunnel junctions (MTJs)
to build FPGA memory blocks. According to [52], MTJbased
BRAMs could increase the FPGA memory capacity
by up to
29 . 5# with the same die size; however, they
would increase the process complexity.
E. DSP Blocks
Table II.
Implementation results for a 2048 × 72-bit 1r+1w RAM using BRAMs,
LUT-RAMs and registers on Stratix IV.
BRAMs
Implementation
144kb BRAMs
9kb BRAMs
LUT-RAM
Registers
20
half-ALM 9k
6597
165155
IEEE CIRCUITS AND SYSTEMS MAGAZINE
18
144k Area (mm2)
1
0.22 (1.0×)
0.41 (1.9×)
2.81 (12.8×)
68.8 (313×)
Freq. (Mhz)
336 (1.0×)
497 (1.5×)
134 (0.4×)
129 (0.4×)
Initially the only dedicated arithmetic
circuits in commercial FPGA
architectures were carry chains
to implement efficient adders, as
discussed in Section III-A. Thus multipliers
had to be implemented in
the soft logic using LUTs and carry
chains, incurring a substantial area
and delay penalty. As high-multiplier-density
signal processing
SECOND QUARTER 2021
Memory Bits Per LE
IEEE Circuits and Systems Magazine - Q2 2021

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