IEEE Circuits and Systems Magazine - Q2 2021 - 91

how actor-oriented components interact. A composition
of actors composed in a particular domain also defines
an actor-oriented component interface, naturally leading
to a hierarchical design methodology. Top-level components
in the hierarchy represent significant portions
of a design in a relatively abstract and coarse-grained
way, while lower-level components typically represent
smaller portions of a design in a more detailed fashion.
MLIR [76] is a rapidly maturing compiler infrastructure
focused on building and transforming abstractions.
MLIR allows tools to be built with a wide variety of abstractions,
called dialects. MLIR dialects can be composed
in arbitrary ways, allowing the description of heterogeneous
systems. MLIR also provides infrastructure
to transform dialects in various ways, enabling compilation
flows from domain-specific to target-specific
abstractions [29]. The rest of this section provides an
overview of how we are leveraging MLIR instruction to
build next-generation domain-specific tooling for Xilinx
Versal devices.
A. MLIR Programming
of AI Engine Devices
We start at the lowest levels of abstraction
with a target-specific abstraction
for Xilinx Versal devices.
Although we focus on device abstractions
for the AI Engine portion of
the device, there is nothing fundamentally
preventing similar representation
of the programmable logic
portion of the device. The MLIR abstraction
uses multiple MLIR operations
to represent different modules
in a device. For example, an AIE.
core operation encapsulates the
code that runs on a single AI Engine
core. An AIE.buffer operation
represents a buffer stored in tile
memory. An AIE.lock operation
represents a lock that can be accessed
from a core or by a DMA.
These operations all reference an
AIE.tile operation, which represents
a physical location in the device.
Similar operations represent
other aspects of the architecture,
such as switchboxes and DMAs. A
simple MLIR program representing
communication between two cores
is shown in Figure 15.
Code generation for the MLIR device
dialect is relatively straightSECOND
QUARTER 2021
forward, since there is a direct correspondence between
the structure of the MLIR code and the structure
of the hardware. The code inside each core is lowered
to the MLIR LLVM dialect using standard lowerings
Domain-Specific
Transforms
Domain-Specific
Abstractions
Generic Transforms
Target-Specific
Transforms
Generic Abstractions
Target-Specific
Abstractions
Figure 14. The hourglass model of compilers. Note that while
we would prefer to maximize the usage of generic, domainindependent
abstractions and transformations, in some cases
it is useful to include domain-specific and target-specific
transformations on domain-independent abstractions.
module @two_cores{
%tile13= AIE.tile(1,3)
%tile14= AIE.tile(1,4)
%buf13_0= AIE.buffer(%tile13)
{ sym_name= " a " }: memref<256xi32>
%buf13_1= AIE.buffer(%tile13)
{ sym_name= " b " }: memref<256xi32>
%buf14_0= AIE.buffer(%tile14)
{ sym_name= " c " }: memref<256xi32>
%lock13_3= AIE.lock(%tile13,3)
%lock13_5= AIE.lock(%tile13,5)
%lock14_7= AIE.lock(%tile14,7)
%core13= AIE.core(%tile13){
AIE.useLock(%lock13_3, " Acquire " ,1,0)
AIE.useLock(%lock13_5, " Acquire " ,0,0)
%idx1= constant3: index
%val1= load %buf13_0[%idx1]: memref<256xi32>
%idx2= constant5: index
store %val1, %buf13_1[%idx2]: memref<256xi32>
AIE.useLock(%lock13_3, " Release " ,0,0)
AIE.useLock(%lock13_5, " Release " ,1,0)
AIE.end
}
%core14= AIE.core(%tile14){
AIE.useLock(%lock13_5, " Acquire " ,1,0)
AIE.useLock(%lock14_7, " Acquire " ,0,0)
%idx1= constant5: index
%val1= load %buf13_1[%idx1]: memref<256xi32>
%idx2= constant3: index
store %val1, %buf14_0[%idx2]: memref<256xi32>
AIE.useLock(%lock13_5, " Release " ,0,0)
AIE.useLock(%lock14_7, " Release " ,1,0)
AIE.end
}
}
Figure 15. Low-level code for an AI Engine design. The code inside each core first acquires
locks associated with the buffers that will be accessed, then performs some computation
that reads and writes from those buffers, and lastly releases the associated locks.
Computation can be represented by any MLIR dialect that can be lowered to LLVM.
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