IEEE Solid-State Circuits Magazine - Fall 2015 - 48

Data Rate (Gb/s)

100

Y
x/4

PCIe
OIF/CEI
Fiber Channel
Ethernet
PON
CPRI

1
2000 2002 2004 2006 2008 2010 2012 2014 2016
Years
Figure 1: Wireline data rates over the years.

SR specified the channel to be shorter than 200 mm with one connector
while CEI-6G LR specified the channel
up to 1 m with two connectors.
In addition to the channel specifications, CEI-6G specifies transmitter, receiver, and channel for 6 Gb/s
applications for backplanes, chip-tochip, and optical modules. Figure 2
shows the example transmitter and
receiver masks. Specific values can
be found in [1].
Almost at the same time, the
CEI-11G standard uses a similar
approach as CEI-6G to specify channel
compliance at 11 Gb/s. CEI-11G-LR/
MR specifies a through channel and
associated dominant crosstalk aggressors. They are compliant if, for both
the specified reference transmitter
and receiver, the signal conforms to
the defined eye masks and does not

_X
1
1.
0

0
-R_Y 1
-R_Y 2

1⋅
T

_X
2

-T_Y 1
-T_Y 2

R_Y 1

Time (UI)
(a)
Figure 2: The CEI-6G TX and RX masks.

fa l l 2 0 15

IEEE SOLID-STATE CIRCUITS MAGAZINE

R
_X
1
0.
1⋅ 5
R
_X
1
1⋅
R
_X
1
1.
0

R_Y 2

0.
0

Amplitude (mV)

T_Y 2
T_Y 1

0.
0
T_
X1
T_
X2

Amplitude (mV)

and module vendors, connector vendors, and system houses so all parties can design their portion ahead
of time, which is critical as most of
the system and transceiver development takes months or even years. It
is impractical to serialize the development efforts.
The specifications also evolve with
data rates. For example, the reach
used to be dictated by the physical
distance demanded by the size of the
chassis. Typically, 1 m is required for
the distance to connect between two
destinations, and the transceiver vendor has to design based on this nonelectrical requirement. The example
standard that fits this is CEI-6G. CEI
[1] includes transceiver to framer interface (SFI), system packet interface
(SPI), time-division multiplexing-fabric to framer interface (TFI). CEI-6G

Time (UI)
(b)

exceed the defined jitter using the
StatEye method [2]. StatEye is an Open
Source physical layer simulation tool
that can help system engineers budget the link. It is based on the theory that, for a known channel pulse
response, a pure random data stream,
and a finite number of cursors, each
possible combination of cursors can
superimpose each with equal probability. The StatEye method can further
incorporate transmitter and receiver
behavioral models catered to different
standard CEI applications. It is a fast
method to assess transceiver behavior but it is based on the fact that
the channel, including circuit components, specifically receiver front-end,
is linear, which poses the limitation
on the tool because as the speed goes
higher, the nonlinear effect of the circuits, specifically in receiver, must be
accounted for correctly.
The receiver mask described is
taken at the receiver input for CEI-6G
and CEI-11G. However, as the data
rate approaches 10 Gb/s, the received
eye usually is closed and most of the
transceivers employ sophisticated
equalization techniques inside the
receiver, such as continuous time linear equalizer (CTLE), automatic gain
control (AGC), and decision feedback
equalizer (DFE) to open up the eye before the slicers. Moreover, at 10 Gb/s,
it becomes clear that the transceiver
circuits are better when designed targeting a certain channel loss (in dB)
since the peaking circuits (CTLE) have
gain parameters in the design specification. As a result, one of the most
popular 10G specifications-10GBaseKR [3]-provides a series of masks for
insertion loss (IL), IL to crosstalk ratio
(ICR), return loss (RL), and IL deviation
(ILD), all in dB.
Figure 3 overlays three example
backplane channels targeting 10G-KR
applications on top of the IL mask.
Two of the channels have their channel loss drops smoothly over the
frequency range, even beyond the
Nyquist, as specified by the mask.
These are high confidence channels
as they were optimized specifically
for 10G applications. Between CTLE

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015