IEEE Solid-State Circuits Magazine - Fall 2015 - 57

Memory Access and
Data Transfer Between Chips
Energy for memory access is two to
three orders of magnitude higher
than that for compute operations
even if the memory is located in an
on-chip cache [6-8]. However, the
switching energies of the memory
cells and sense amplifiers for static
random-access memories (SRAMs)
and dynamic random-access memories (DRAMs) are not significantly
larger than those for logic circuits.
The high energy for memory access
is due to the overhead associated
with transferring data between
the target cells and the outside.
Historically, memories have been
optimized to maximize the area

1,000

Wire
Gate Load
Wire [6]
Gate Load [6]

1

0.1

0.01

90

65

45

32
22
14
Technology (nm)

7

Like computing performance, power efficiency has
also increased exponentially,
doubling every 1.52 years.
efficiency of memory cells, and so
their internal data-transfer energy
has not always been minimized.
When an off-chip DRAM is accessed, signal transfer will take
place between chips, making the required energy even greater. Energy
consumed inside a memory may be
seen as a type of data-transfer energy, and from here on it will, together
with the energy needed for memory
access and the transfer of signals
between chips, be collectively called

10
1

data-transfer energy. Note that, in
line with this convention, the energy associated with data motion
and memory access in a processor
chip will be classified as data-motion energy.
The ratio between the bandwidth
of data transfer B and performance
F (= B/F) is a quantity that affects
the frequency of data-transfer events
outside a chip. Processor cores have
high bandwidth requirements in proportion to their performance F, but

1,000
Technology (nm)

100

100

10
×0.7/Two Years

×2/Two Years

19
96
19
98
20
00
20
02
20
04
20
06
20
08
20
10
20
12
20
14
20
16
20
18
20
20

1

19
96
19
98
20
00
20
02
20
04
20
06
20
08
20
10
20
12
20
14
20
16
20
18
20
20

1

0.1
Year
(a)

10

Figure 6: Wiring energy and gate fan-in energy.

×1.4/Two Years

ISSCC 1996-2015
Bandwidth (Gb/s)

10

Normalized Energy

to the assumption that the wiring
capacitance per computer-aided
design grid is constant for complex
designs beyond 90 nm (Figure 5).
Figure 6 has been obtained by
plotting the associated switching
energy (wiring energy and gate fanin energy) under the same assumption. The resulting wiring energy
and gate-load energy agree reasonably well with [6].
Figure 6 shows that the energy
consumed within the chip for data
transfer is dominant in complex
compute circuits for finer technologies because the wire capacitance
per grid is constant regardless of
scaling, while the gate capacitance
is reduced by scaling.

Year
(b)

Figure 7: The trends in wireline transceivers for (a) data rate per pins and (b) technology.

IEEE SOLID-STATE CIRCUITS MAGAZINE

fa l l 2 0 15

57



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Fall 2015

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