IEEE Solid-State Circuits Magazine - Fall 2015 - 89

gm
IDS

1
nUT

minimum value, below which the current
I DS hardly decreases. For high-frequency
applications, IC = 1/m 2c or (L/20 nm)2
is the maximum value. For channel
lengths below about 20 nm, these two
values coincide at IC = (L/20 nm)2, which
becomes smaller than unity for even
smaller channel lengths.

L = 20 nm
1/2

L < 20 nm

L > 20 nm
-1

λc
nUT
IC

IDS
1

gmnUT

gmnUT
λc

1/2

References

IC

IDSsp
gmnUT

-1
gmnUTλc

-1/2
1/λc2

1

1/λc

IC

Figure 8: Normalized (a) g m /I DS, (b) I DS, and (c) I DSsp versus IC for different channel lengths.

increase more than in velocity saturation. Indeed the expressions of g m
in both regions contain both WC ox,
but the one in weak inversion has L
in the denominator! Therefore, the
dependency of g m on the channel
length L is much stronger in weak
inversion than in velocity saturation.

The peak value of fT # g m /I DS occurs
clearly at IC = 1/m 2c .
This same curve in Figure 7(d) also
shows that higher values of the IC are
limited by physics, not technology.
The right-hand side asymptote is set
by parameters such as U T , n, and the
mobility and not by the channel length

The EKV/BSIM6 models are ideally suited
to simplify the design procedure of a
single-stage amplifier.
The product of fT # g m /I DS is
added as well in Figure 7. It is often
used as an FOM for RF applications
[8]. The optimum biasing point is
IC = 1/m 2c = (L/20 nm) 2 .
It
then
becomes smaller than unity for even
smaller channel lengths.
The same conclusions can be
drawn when Figure 6 is repeated for
channel lengths, which are smaller
than 20 nm, as shown in Figure 8. For
example, for 5 nm CMOS, m c = 4 and
1/m 2c = (L/20 nm) 2 = 1/16 or about
0.06. This is the optimum value for
the IC, now for both low-power and
high-frequency operation together.
This is also evidenced by Figure 7(d).

[1] S. Damaraju, V. George, S.Jahagirdar,
T.Khondker, R. Milstrey, S.Sarkar, S. Siers,
I. Stolero, and A.Subbiah, "A 22 nm IA
multi-CPU and GPU system-on-chip," in
IEEE Int. Solid-State Circuits Conf. Dig.
Tech. Papers (ISSCC), 2012, pp. 56-57.
[2] W. Sansen, "Analog CMOS from 5 micrometer to 5 nanometer," in Proc. ISSCC 2015,
pp. 22-27.
[3] A. Steegen, "Logic scaling beyond 10 nm,
a power-performance-area-cost trade
off," in Proc. ESSCIRC 2014, pp. 20-22.
[4] C. Enz and E. Vittoz, Charge Based MOS Transistor Modeling. Hoboken, NJ: Wiley, 2006.
[5] W. Sansen, Analog Design Essentials. New
York: Springer, 2006.
[6] H. Shichman and D. Hodges, "Modeling
and simulation of insulated-gate fieldeffect transistor switching circuits," in
IEEE J. Solid-State Circuits, vol. 3, no. 3, pp.
285-289, Sept. 1968.
[7] W. Sansen, "Analog design procedures for
channel lengths down to 20 nm," in Proc.
ICECS 2013, pp. 337-340.
[8] T. Taris, J. Begueret, and Y. Deval, "A
60 μW LNA for 2.4 GHz wire-less sensors network applications," in Proc. RFIC
Symp., 2011, pp. 1-4.

About the Author

L. At IC = 1, its value is about 24 THz/V.
Parameter U T cannot be changed.
Parameter n can be reduced to unity in
gate-all-around devices such as in FinFETs [3]. The mobility can be increased
by adopting other more exotic materials such as germanium [3]. This is part
of the future, however.

Conclusions
The EKV/BSIM6 models are ideally
suited to simplify the design procedure
of a single-stage amplifier because the
normalized current, or inversion coefficient, is used as a design variable. It
can be concluded that for minimum
power consumption, IC = 1 is about the

Willy Sansen (willy.sansen@esat.kuleuven.be) received a Ph.D. degree
from the University of California,
Berkeley, in 1972. Since 1980, he has
been full professor at the Catholic
University of Leuven (KU Leuven),
Belgium. From 1984 to 2008, he has
headed the ESAT-MICAS. He has supervised 64 Ph.D. theses and has
(co)authored more than 650 publications and 15 books, including the
PowerPoint slide-based book Analog
Design Essentials (Springer 2006). He
has been involved in several spinoffs
of the KU Leuven and is a member of
several boards of directors. He was
program chair of the ISSCC 2002 and
president of the IEEE Solid-State Circuits Society in 2008-2009. He received the D.O. Pederson Award in
2011. He is a Life Fellow of the IEEE.

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