IEEE Solid-State Circuits Magazine - Summer 2016 - 48

The key ideas behind XMODEL can trace
their roots to Prof. Horowitz's early works
dated almost 33 years ago.

for MOS Circuits" published in 1984
[2], Prof. Horowitz further extended
the method to handle circuits that
require two time constants for higher
accuracy or include nonlinear devices
such as transistors.
The Elmore delay is a simple way
to estimate the delay of an RC network
by approximating its waveform as an
exponential function. For instance,
a signal rising from zero to VDD is
approximated as
(1)

V ^ t h . VDD $ ^1 - exp ^-t/xhh,

where x is called the time constant
of the waveform. Once x that best
approximates the actual waveform
is known, the delay D, i.e., the time
for this signal to reach the half-way
point between zero and VDD , can be
computed as
(2)

D = ln ^2 h $ x . 0.7 x.

The Elmore delay method determines
this time constant x so that the total
integrated area of the waveform V (t)
is equal to that of the single-exponential waveform. This is, in general,
called moment matching since the total
area corresponds to the first moment
of the waveform. What is remarkable

is that such x can be found almost by
inspecting the RC network using the following formula:
x Elmore = / R i, k C i,

(3)

where C i denotes the capacitance
on node i and R i, k is the total resistance that the path from the input
root to node i shares with the path
from the input root to the final output (node k ). Considering the RC network shown in Figure 1, which is an
excerpt from Prof. Horowitz's Ph.D.
thesis, the Elmore delay D Elmore can
be computed as
D Elmore = 0.7 $ x Elmore
= 0.7 $ (R 1 C 1 + R 1 C 2
+ (R 1 + R 3) C 3
+ (R 1 + R 3 + R 4) C 4 .

(4)

Note that the resistance multiplied
with C 2 is R 1 instead of R 1 + R 2,
since only R 1 is in common between
the path from root to node 2 and the
path from the root to node 4.
The key concept that led to the derivation of this Elmore delay expression
was that the waveforms of most linear
and nonlinear circuits can be sufficiently approximated using just one or
two exponential functions, of which

2
C2

Root
oot
R1

R3
C1

R4
C3

Output
C4

Figure 1: An example of estimating delay of an RC network using Elmore delay. (An excerpt
from [2], used with permission.)

s u m m e r 2 0 16

IEEE SOLID-STATE CIRCUITS MAGAZINE

characteristics can be described by a
handful of parameters. Once you have
this simple functional expression for
the waveform, you can analytically
calculate its properties, such as delay
and rise/fall times, of which expressions can provide invaluable guidance
to designers. For instance, the analytical expression of delay in the form of
RC products tells us that the delay is
contributed by two major factors: the
driving resistance and load capacitance. This insight laid the foundation
for the method of logical effort [3], a
systematic way of sizing a chain of
logic gates for minimum delay.

Switch-Level Circuit Simulator
With his simple yet powerful delay
estimation method, Prof. Horowitz
retrofitted RSIM, a switch-level simulator developed by Christopher J.
Terman at the Massachusetts Institute
of Technology [4] to enhance the accuracy of its delay estimation. The simulator was further extended to IRSIM by
his former Ph.D. student, Arturo Salz,
with an incremental simulation capability [5]. IRSIM is still widely used as
an open-source digital timing analysis
tool in many undergraduate/graduatelevel very-large-scale integration
courses (Figure 2).
A switch-level simulator aims to strike
a balance between a gate-level simulator like Verilog and a circuit-level
simulator like SPICE. A gate-level simulator describes a digital system as a network of logic gates where their signals
propagate in one direction only with
Boolean values. Such a representation
enables a fast event-driven simulation
but poses a limitation that the delay
of each logic gate must be precharacterized based on its loading condition
since the simulator itself cannot compute the delay. Also, it cannot handle
some pass-transistor logic gates in
which the signals may propagate in
both directions. On the other hand, a
circuit-level simulator like SPICE can
simulate an arbitrary circuit network
of linear and nonlinear devices. SPICE
makes no assumption regarding the signal's propagation direction, and hence it
can accurately simulate the transient

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