IEEE Circuits and Systems Magazine - Q1 2021 - 26

technologies to meet the demands of extensive data
processing for current and next-generation computing.
This subsection discusses how nonconventional arithmetic plays an important role in memory technologies,
namely, to perform PIM.
Hybrid memories combine CMOS with non-CMOS
devices in a single chip as one alternative to existing
semiconductor memories [98]. These memories use
nanowires, carbon nanotubes, molecules and other technologies to design the memory cell arrays, while CMOS
devices are used to form the peripheral circuitry. One of
the first articles to investigate the application of RRNS to
improve the reliability of hybrid memories was published
in 2011 [98]. A new RRNS code is proposed for a 6-moduli
set, where two are nonredundant moduli and four are
redundant moduli and maximum likelihood decoding is
applied to resolve the ambiguity that occurs for less than
10% of the decoded data.
The CREEPY core, referred to in Section II-B, also
adopts RRNS to achieve computational error correction
for new devices with signal energies approaching the
k B T noise floor [53], such as the Ferroelectric Transistors (FEFET) [99]. The 4T nonvolatile differential memory based on FEFETs is a good energy-efficient candidate
for PIM [100].
Memristors, a contraction of the terms 'memory' and
'resistor', are devices that behave similar to a nonlinear
resistor with memory [101]. Memristors can be used
to combine data storage and computation in memory,
thus enabling non-von Neumann PIM architectures
[102]. CNNs have been fully hardware-implemented using memristor crossbars, which are cross-point arrays
with a memristor device at each intersection [103]. The
processing-in-memory-and-storage (PIMS) project also
adopts the RRNS for memristor-based technologies
[104]. Moreover, it has been shown that SC is adequate

h0
+1
A
+2
-1 J

Y

h2
-2

+2

h = +1

+1

-2

0
J = -1
+2

-1 +2
0 +2
+2 0

B
+1
h1

(a)

(b)

Figure 16. Boltzmann Machine structure for the AND gate
[78]: three nodes, those denoted A and B refer to binary
inputs, and Y the output. (a) Boltzmann structure. (b) h
and J (38).

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IEEE CIRCUITS AND SYSTEMS MAGAZINE

to perform PIM on nanoscale memristor crossbars, allowing the extension of the flow-based crossbar computing approach to approximate stochastic computing
[105]. Applications of in-memory stochastic computing
to a gradient descent solver and a k-means clustering
processor can be found in [57].
An end-to-end brain-inspired HDC nanosystem using the heterogeneous integration of multiple emerging
nanotechnologies was proposed in [106]. It uses monolithic 3D integration of Carbon Nanotube Field-Effect
Transistors (CNFETs) and Resistive Random-Access
Memory (RRAM). Due to their low fabrication temperature, (1,952) CNFETs and (224) RRAM cells are integrated with fine-grained and dense vertical connections
between computation and storage layers. Integrating
RRAM and CNFETs allows creating area- and energyefficient circuits for HDC.
Multi-level cell (MLC) is used to store multiple bits
in a single RRAM cell to reduce the hardware overhead.
However, the accuracy of ANNs deteriorates more due
to resistance variations, which is quite relevant in binary coding. The error-tolerance feature of SC can also
be explored to mitigate the reliability problem of RRAM
MLC technology [107].
D. Invertible Logic Circuits
Invertible logic provides a reverse mode for which
the output is fixed and the inputs take on values consistent with the output [78]. It is less restrictive than
reversible logic. For example, the two-input OR logic
gate is invertible if when the output is kept at c = 1,
the inputs ^a, b h alternate equally, with a probability
of 33%, between the values ^1, 1 h, ^0, 1 h, and ^1, 0 h, but
it is not reversible.
Boltzmann machine structures [83] are underlying
structures that have been proposed to design invertible logic circuits [78]. These machines can be represented as networks or graphs of simple processing elements interconnected (e.g., Fig. 16(a) for a two-input gate
Y = A / B ) with signals taking the binary values +1 or 1.
Every node in the undirected graph is fully connected to
all others through bidirectional links, and an individual
bias value is assigned to each node. The binary state
and ith node output ^m i h are computed by (38): after
calculating the weighted sum of all input connections
(matrix J ) and adding the bias terms (h), the nonlinear
activation function ( tanh) is applied. A noise source
rnd ^-1, +1 h (uniformly distributed random real number between -1 and +1) is introduced to avoid getting
trapped in local minima, and finally, the sign function
(sgn) provides the binary outputs +1 or -1. I 0 is a scaling factor (an inverse pseudo-temperature). States are
categorized as valid and invalid states. If the nodes are
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