single chip human sensing radar. Aimed at integration and size compactness, validations of this radar were performed on a target located 1 m away in different scenarios. Next, the work in [52] proposed a digital closed loop compensation architecture for LFMCW. It is aimed at solving nonlinear distortions caused by the analogue modules, which deteriorates detection accuracy. Despite not being specifically developed for vital sign de- tection, such design can be adapted for such purpose, especially when implemented using an FPGA. Besides that, a pulse noise generator is proposed to be implemented to jam a linear frequency modulated pulse compression (LFM-PC) radar in [53]. Finally, a new signal processing module and algorithm for target detection is introduced and implemented on a FPGA on a FMCW radar in [54]. It is capable to be used to extract range, Dual Rx Signal Chain USRP-2954R I Rx2 I Rx1 ADC Rx Antenna ADC Q Rx2 120 MS/s Host Computer Q Rx1 PCIe Interface 0° 90° Target ADC FPGA Digital Baseband Tx Signal Chain I Tx Q Tx DAC 120 MS/s 0° 90° Tx Antenna Power Splitter DAC Figure 10. Pulse radar system in [40]. Licensed under Creative Commons attribution licenses https://creativecommons.org/ licenses/by/4.0/ Coarse Range Bin DLL × 2 Waveform Generator Ch1 DSP Ch2 ADC T&H S&H T&H t T&H T&H S&H t Ch16 T&H Ch2 VGA S&H T&H t Tx Ch1 Fine Range Bin VGA Driver Rx LNA Ch16 UWB Radar Chip Figure 11. CMOS UWB radar diagram [45] © 2016 IEEE. FIRST QUARTER 2021 IEEE CIRCUITS AND SYSTEMS MAGAZINE 53https://creativecommons.org/licenses/by/4.0/ https://creativecommons.org/licenses/by/4.0/