IEEE Solid-States Circuits Magazine - Summer 2018 - 19

An alternative to resilient designs is a unique
class of adaptive circuits that specifically
address the response-time constraint in the
traditional adaptive designs.
at an FMAX of 1.45 GHz at 1.0 V. When
a 10% VDD droop occurs during program execution, the FMAX reduces to
1.26 GHz. The shaded region in Figure 3 represents the FCLK guard band
for a 10% VDD droop in the conventional design. Enabling EDS or TRC
designs allow the detection and correction of errors, resulting in a higher
FCLK and throughput. The optimal FCLK
for the resilient designs (1.46 GHz for
the EDS circuit and 1.42 GHz for the
TRC) occurs at the point of maximum
throughput. Pushing the FCLK beyond
this point reduces the throughput
because the increasing number of recovery cycles outweighs the benefit
of a larger FCLK. At 1.0 V, the EDS and
TRC designs improve throughput by
16 and 12%, respectively. Since the
EDS design detects actual criticalpath errors, the throughput benefit
results from detecting and correcting
VDD-droop errors as well as operat-

ing faster than infrequently activated
slow paths. By comparison, the TRC
design provides a smaller throughput
at 1.0 V since the slowest path in the
processor limits the TRC delay, and
unnecessary recovery cycles occur
when a critical path is not activated
in the cycle with the TRC failure.
Although the EDS design provides
a larger benefit at 1.0 V, min-delay
constraints limit the maximum error-detection window and the corresponding potential throughput
gain. As highlighted in Figure 4, the
EDS design can mitigate only a portion of the FCLK guard band at 0.8
and 0.6 V when the dynamic delay
variation exceeds the error-detection window. In contrast, processor
min-delay constraints do not limit
the error-detection window for the
TRC design, allowing the TRC to
capture a wider range of dynamic
delay variation.

Normalized Throughput

1.3
1.2
1.1

FCLK
Conventional Guard Band
Maximum
Throughput

Resilient: EDS
Maximum
Throughput

1
0.9
0.8

Recovery Cycles (%)

design employs a data-path latch, pathtiming constraints remain from rising
clock edge to rising clock edge (i.e., FF
based), with an error-detection window
during the high clock phase to ensure
that late-arriving input does not affect
the path maximum-delay (max-delay)
constraint for adjoining fan-out paths
in subsequent pipeline stages.
There are many EDS designs [7]-
[17] with various tradeoffs. Most designs either double-sample the input
data similarly to the DSTB circuit or
detect the input data transition during the high clock phase. The fundamental tradeoff in any EDS circuit is
the path max-delay versus minimumdelay (min-delay) constraints. For
DSTB, the high clock phase defines the
error-detection window. The errordetection window relaxes the max-delay constraint to enable a potentially
higher FCLK or lower VDD at the cost
of penalizing the min-delay requirements, resulting in more min-delay
buffers. The post-silicon calibration
of the high clock phase with a dutycycle control circuit ensures protection from min-delay violations.
In comparison to the embedded
EDS design, the TRC is a less-intrusive
error-detection technique [13] that
does not affect critical-path timing.
The TRC consists of a toggle FF and a
configurable delay chain. The toggle
FF switches the input to the delay
chain every cycle. The TRC output
drives an EDS circuit to detect timing-margin failures due to dynamic
parameter variations. As illustrated
in Figure 2, the design inserts a TRC
adjacent to each pipeline stage. By
calibrating each TRC during post-silicon testing, the TRC delays track the
worst-case critical-path delay while
minimizing the effect of process variations. If a dynamic variation induces
a TRC timing-margin failure, the TRC
generates an error signal, representing the single pipeline-error signal to
isolate the error from corrupting the
architecture state and to initiate the
error recovery, as described for the
embedded EDS design.
In Figure 3, the conventional design executes a benchmark program

Resilient: TRC
Maximum
Throughput

VDD = 1 V
10% VDD Droop
EDS

101
100
10-1
10-2
10-3
10-4
1.1

TRC Guard Band
+ Path Activation
TRC

1.2

Unnecessary
Recovery
1.3
1.4
1.5
Clock Frequency (GHz)

1.6

1.7

FIGURE 3: The measured throughput and recovery cycles versus FCLK. (Image from [13].)

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IEEE Solid-States Circuits Magazine - Summer 2018

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