IEEE Solid-States Circuits Magazine - Summer 2018 - 32

I/O Serializer

TCSPC/PC
7 bit

12.3 mm

Start
Stop

160 × 128-Pixel
Array
3 bit

PLL
I2C

Encoder

Global CK

I/O Serializer
11.0 mm

Counter
× 16
T

Front End
Interpolator
× 16
D
CK[0:15]

Encoder

4 bit

TCSPC/PC

6 bit

Figure 13: A 160 × 128-pixel array with in-pixel TDC for TCSPC or photon-counting applications. (Image from [7].) I/O: input/output; PC:
photon counting; PLL: phase-locked loop.

Figure 14: A 32 × 32-pixel array with TDCs and low-noise SPAD for TCSPC applications.
(Image from [12].)

In [12], an extremely low-noise
SPAD (thanks to the customization of
the process) has been included in a
32 × 32-pixel imager. Despite the relatively large technological node (i.e.,
0.35-nm technology), the authors
implemented a per-pixel multiphase
interpolating TDC with 312 ps of resolution in 150-nm pitch with a 3.14%
FF (Figure 14). Also, in this realization, it is possible to select between
the TCSPC or photon-counting mode.
One of the advantages of having lownoise SPADs, in general, is that a relatively smaller number of acquisitions
is needed to construct the TCSPC statistics and overcome the device noise
in terms of DCR.

FLIM Imagers
Fluorescence lifetime imaging typically does not require a full TCSPC
acquisition because the fluorescence
is known to produce single or multiexponential decays. Therefore, time-

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gating is perfectly suitable and far
more efficient than TCSPC, needing to
measure just two windows for a single exponential and four windows for
double exponential characteristics.
Furthermore, the faint fluorescent
signals make the FF an extremely important parameter, favoring solutions
with area-efficient implementation. In
[11], an all-analog solution has been
realized with an in-pixel analog counter that can be triggered by the SPAD
pulse only during the observation
window. As depicted in Figure 15, the
very small number of transistors allowed a remarkable 20.8% fill factor in
25-nm pitch with a 0.35-nm technology, with a minimum gating window
of 1.1 ns. This could be achieved by
using only NMOS devices, thus avoiding the nwell spacing rules and at the
same time allowing the deep-nwell
sharing between SPADs. A step further in optimization has been made
in [10], where just 7 NMOS and a MOS

IEEE SOLID-STATE CIRCUITS MAGAZINE

capacitor allowed time-gated analog
counting, with a FF of 21% in just
15-nm pitch with the same 0.35-nm
technology, and a minimum observation window of 750 ps. An additional
feature that aims at reducing the disadvantages of the analog approach is
the presence of a column-level singleslope analog-to-digital converter; this
implementation exploits, as ramp
generator, the pixel itself, thus virtually canceling any nonuniformity and
nonlinearity thanks to a self-referenced conversion (Figure 16).

TOF Imagers
Another popular application for SPADs
is direct TOF imaging, where every pixel needs to capture and time-stamp the
returning photons emitted by a source
and reflected back by the scene. One
of the biggest challenges to address
is the background light, unavoidably
present in the scene, that is virtually undistinguishable from the signal
photons. A clever solution has been
implemented in [14], where 12 SPADs
have been combined in a macropixel
that performs a coincidence detection.
As depicted in Figure 17, the linear arrangement is used in a scanning system to achieve ten frames per second
for a 340 × 96-pixel image resolution.
The coincidence circuit looks for temporal correlations between pulses
of the 12 SPADs, triggering the TDCs
only when more than a given number of pulses is detected within the

IEEE Solid-States Circuits Magazine - Summer 2018

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