IEEE Circuits and Systems Magazine - Q4 2022 - 28

network weights are stored. In contrast to digital architectures
that spend significant energy to read operands
from memory, in situ computation eliminates the need to
move weight data between processing elements. Within
an array, individual analog MACs can also be conducted
at a lower energy, higher density, and greater parallelism
than digital MACs [45]. Due to these potential advantages,
in situ MVM has attracted significant research
attention for neural network inference [6], [11], [14], [42],
[49], [56], as well as other applications [9], [18], [58].
Figure 1(a). shows a conceptual example of an in situ
MVM array that computes

yx= W . The memory cell
conductances G are set proportional to the values of
W, and the rows are driven by input voltages
are proportional to

V that

x. Each cell's current is an analog
product of its conductance Gij and the applied voltage
Vi. Kirchoff's law then accumulates these products on
the bit line (column) current Ij to form the dot product.
The analog dot products are subsequently quantized
using an ADC.
In situ MVM has been demonstrated using a wide
variety of memory cell technologies [55], [61], [68].
Fig. 1(b) shows a 1T1R (1 transistor, 1 resistor) cell,
which performs multiplication using Ohm's law across a
two-terminal programmable resistor, such as a resistive
random access memory (ReRAM) or phase change
memory (PCM) device. During an MVM, the transistor
is transparent. Fig. 1(c) shows an alternative cell design,
more typically used with transistor-based memories
such as flash memory [5], [20], [24], where a select transistor
uses the input to gate the flow of current through
the memory element (green).
The conceptual example in Fig. 1 elides a number
of practical implementation details. Prior work has
proposed multiple approaches for data representation
(W and

x) that differ from the mapping in Fig. 1.
Table 1 summarizes the design choices made by several
recently proposed in situ MVM accelerators, which are
explained below. A recent review of analog inference
accelerators can be found in Xiao et al. [62].
2.1. Weight Bit Slicing Versus Unsliced Weights
To represent matrices with more bits than can be reliably
programmed in a device, many systems use bit
slicing [9]. In bit slicing, the bit representation of each
matrix element is divided into multiple slices, and the
results of bit sliced MVMs are combined via shift-andadd
(S&A) reduction [9], [21], [56]. Equation 1 shows
how a matrix of 6-bit integers can be divided into two
slices of three bits each.
ª 30
«¬
12 58
29 50
º
»¼
2
ª
«¬
17
36
º
»¼
2
ª
«¬
42
52
º
»¼
(1)
Bit slicing admits the use of high-precision weights
with more possible values than the number of programmable
levels in a memory device. In particular, it allows
the use of inherently binary memories such as SRAM
that cannot otherwise implement multi-bit weights [17].
Many accelerators use bit slicing as a way to tolerate
analog memory cells with arbitrarily low precision, but
this assumption has not been thoroughly evaluated on
the basis of end-to-end inference accuracy and not just
the weight precision.
To avoid the energy and area overheads of reading,
Figure 1. (a) Execution of an mVm

yx= W within a memory
array. (b) and (c) two implementations of a memory cell that
performs analog multiplication.
Figure 2. conductance program distribution of a memory cell
when used as two different types of memory.
28
IEEE cIrcuIts and systEms magazInE
digitizing and aggregating multiple bit-sliced arrays,
the magnitude of a weight can also be fully encoded
in one device [30], [34]. Unsliced weights ostensibly
require very precise devices; however, for inference
it can be sufficient to use analog memory cells not
as multi-bit digital memories as in Fig. 2(a), but as
approximate memories shown in Fig. 2(b). The conductance
state of an analog cell has a nonzero width
due to process variations and noise. When used as
a multi-bit digital memory, digital levels are mapped
to states that have nearly zero overlap to enable statistically
reliable readout of a single cell. When used
as approximate memory, many more digital levels are
mapped to the same conductance range by allowing
fourth quartEr 2022
IEEE Circuits and Systems Magazine - Q4 2022

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