IEEE Circuits and Systems Magazine - Q4 2022 - 34

fully-connected layer to one or more memory arrays,
representing different bit slices and matrix partitions,
according to a chosen mapping scheme. Every analog
MAC is simulated during inference. Digital operations
such as the S&A aggregation of weight slices, ReLU activation,
and inter-layer communication are assumed to
be error-free. Convolutions are unrolled into a sequence
of sliding window MVMs, executed on arrays of size
KxKyNic × Noc as described by Shafiee et al. [56] (Kx × Ky is
the 2D filter size, Nic and Noc are input and output channel
dimensions). All simulations were conducted on
Nvidia V100 GPUs.
The modeling of random cell programming errors,
ADC quantization, and parasitic voltage drops are
described in Sections 5, 6, and 8, respectively, where the
accuracy impact of each non-ideality is analyzed separately.
This work does not explicitly study the effect of
cycle-to-cycle read noise, which is similar to that of programming
errors. Read noise has a weaker effect than

IEEE Circuits and Systems Magazine - Q4 2022

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