# IEEE Circuits and Systems Magazine - Q1 2018 - 32

```Input Voltage

VI

Vertical Bit Line
BLj

VI,1
VI,2
VI,3

Conductance
Between WL and BL

VI,i

WLi

VI,i+1

Horizontal
Word Line

VI,N

Resistor

VO,1

VO,2

VO,3

VO,j-

VO,j

rs

rs

rs

rs

rs

VO,N-1
rs

VO,N

VO

Output Voltage

rs

Single Memristor Device

-

Undoped

Doped

+
ROFF

RON

Figure 2. illustration of a memristor crossbar.

or equivalently,
VO = CVI, C = diag

1

N

i =1

j =1

f * g s + / g ij 4 p

N
i i =1

N

GT ,

(1)

where diag ({x } ) denotes a diagonal matrix with diagonal entries x 1, x 2, f, x N , and G is the conductance
matrix of memristors whose (i, j) th entry is given by g i, j .
In (1), the desired coefficient matrix C can be realized
by adjusting memristor conductivities {g i, j} and the bias
resistor's conductance g s . In order to avoid out-of-range
coefficients in the memristor crossbar, a pre-scaling step
is required to scale all matrix coefficients to fall into the
memristors' conductance range. In this manner, one can
perform matrix-vector multiplications through a preconfigured (or programmed) memristor crossbar.
Reversing the above operation, the memristor crossbar structure can also solve a system of linear equations [6]. Here, we assume that the solution exists and
is unique. It is clear from (1) that if we apply VO on BLs,
then VI on WLs becomes the solution of the linear sys32

ieee circuits and systems magazine

tem described by a pre-configured memristor network.
An appealing property of the memristor-based linear
equation solver is its high computational efficiency,
an astonishing O (1) time complexity [15], since the
matrix-vector multiplication (or its reverse operation)
is performed in a parallel fashion. While this structure
are challenges introduced by the hardware restrictions of memristors. First, in the linear system (1), only
a non-negative coefficient matrix can be mapped onto
memristors. Second, a memristor crossbar is size-limited (e.g., 1024 # 1024 or 2048 # 2048 ) due to manufacturing and performance considerations [10]. Third, a
memristor crossbar suffers from hardware variations
that introduce computational errors while performing
matrix-vector operations. In what follows, we elaborate
on the aforementioned challenges and present some
possible solutions.
Since only non-negative coefficients can be mapped
to memristors, it is essential to design a general mechanism that can deal with negative coefficients. In previous
first quarter 2018

```

# Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q1 2018

Contents
IEEE Circuits and Systems Magazine - Q1 2018 - Cover1
IEEE Circuits and Systems Magazine - Q1 2018 - Cover2
IEEE Circuits and Systems Magazine - Q1 2018 - Contents
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