IEEE Solid-States Circuits Magazine - Summer 2022 - 30

nonlinear distortion specifications
[12], [13]. This supports the assumption
made thus far that all devices in
the stack, MCS, MCAS, SP, and SN, are intended
to always work in saturation.
Before considering a better solution,
some observations are in order.
First, for a single-ended output,
namely, when using only one output
node with a single ZL, the INL plot has
a very pronounced bow shape, introducing
a strong second-order distortion,
along with smaller, higher-order
harmonics. However, with a differential
output, even-order distortion
cancels out, and the INL plot displays
a tamer S-shape curve, indicating a
dominant third-order distortion [12].
It can be proven, after some algebra,
that,
the kth-order odd-harmonic
/
HD ZN Z4kL u
=
ZR s1uu
=+ ~c^h with
distortion is ^h-k 1
[13], [14]. This also means that, in the
common case in which ZL = RL (say,
50 )X and // ,
Ru in the tens of K ,X even if RR /Lu
is small enough at a low frequency,
once the corner-angular frequency
~ c
is reached, third-order nonlinearity
increases with the square of frequency,
as shown in the asymptotic
plots of Figure 7(b). This is not good
news as, in many practical cases,
the corner frequency might only be
of the order of hundreds of megahertz.
This also illustrates in a very
direct way that although static linearity
sets an upper bound for DAC
performance, as signal frequency
increases, the DAC's dynamic linearity
degrades rapidly from its low-frequency
baseline [2].
One possible way to mitigate this
limitation, both at low and high frequencies,
is shown in Figure 8 [14].
As previously stated, the distortion
does not arise from /RR
Lu being insufficiently
small. It does arise from
having a code-dependent equivalent
Zup (respectively, Zun) in parallel with
the load. If we can make the latter
code independent, then the problem
is solved.
In the modified circuit of Figure 8(a),
the load ZL sees the drains of a new
pair of output cascode transistors
MC introduced in each cell, all tied
to the output nodes. If nothing else
was added, the MCs would provide
another level of cascoding, possibly
improving the
RR /Lu
ratio a
bit, yet without solving the eventual
frequency-dependent degradation.
However, two additional small-bias
current sources, Ib, are added to each
cell, which supply a minimum source
current to the MCs, always keeping
them both in strong inversion. Accordingly,
as shown in Figure 8(b),
the MC's gate-source capacitance Cgs is
nearly constant, whether such cascode
flows only Ib (for the branch
where the switch is off) or Ib + Iu
(in the other branch). Then, both
cascodes' drains present a nearly
constant/code-independent impedance
to the load, for all cells, and the
nonlinear distortion is substantially
mitigated in exchange for a benign,
low-pass output filtering. There is
also an output common-mode offset
due to the sum of all the sources Ib,
aptly referred to as keep-alive currents,
which are usually designed to
be roughly 10% of Iu.
Cgs
Zu
S
Ib
VC
MC MC
ZL
(a)
FIGURE 8: Output cascoding for finite impedance mitigation.
30 SUMMER 2022
IEEE SOLID-STATE CIRCUITS MAGAZINE
+-
ZL
c0+
c0-
Ib
VT
(b)
Vgs
Iu
Bias
to Be
Here
Current Sources' Calibration
A DAC's current source array can be
designed to meet specified matching
requirements by suitably sizing the
area of the current source devices,
their overdrive voltages, and the
choice of segmentation [1], [2]. But as
previously pointed out, as a result of
typical process technology parameters,
headroom limitations, and so
on, this can become an overly constrained
optimization problem [15].
This often leads to selecting large
current source devices, which suffer
from large, stray capacitances that
are possibly accompanied by nonnegligible,
stray inductive interconnects.
In short, this approach is unlikely
to yield a compact implementation,
with minimal parasitics (a baseline
requirement for ultrahigh sample
rate) that leave very little residual
design freedom to tackle various
high-frequency challenges [15]. On
the other hand, being able to correct
dc errors in the tail sources, independently
(and automatically) from their
geometry or overdrive voltage, provides
much needed freedom to optimize
device sizing, quiescent point,
segmentation, and so forth for better
high-frequency operation.
Many calibration methods are
based on a rather mature idea [16],
as exemplified in Figure (a). In this
figure, a regular current-steering
cell, consisting, as usual, of the current
source device MCS, cascode MCAS,
and steering pairs controlled by c0+
and c0−, is extended by the introduction
of a few more elements. The desired
total current Iu
is realized as
the sum of two contributions, If and
IEEE Solid-States Circuits Magazine - Summer 2022

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