IEEE Solid-States Circuits Magazine - Winter 2022 - 60

Rxs operating under 1 mW. This includes
a record -124-dBm sensitivity
for a 781-µW Rx that leverages
a coherent frequency-shift-keying
demodulator and integrated 4,192-bit
correlator. Clever techniques to leverage
duty cycling to reduce the average
power without compromising latency
also constitute a recent trend. Selectivity,
or interference rejection, is a
critical metric for all Rxs that operate
in the presence of other incumbent
transmitters. As all RF spectrum
becomes more crowded, adequate
signal-to-interference ratios (SIRs)
and image rejection ratios (IRRs) are
essential for scaling the number of
20
10
-10
-20
-30
-40
-50
-60
-70
-80
150
users that can concurrently occupy a
band. As Figure 9 highlights, recently
published ULP Rxs have steadily advanced
this metric, even at the expense
of sensitivity and power.
Communication Systems:
Wireline Subcommittee
Subcommittee Chair: Yohan Frans,
Xilinx, San Jose, California, USA
Over the past few decades, electrical
and optical interconnects have been
the key components bridging the gap
between the exponentially growing
demand for data bandwidth across
electronic components/systems and
the relatively gradual increase in pin/
cable density. Ranging from handheld
electronics to supercomputers, wireline
data communication bandwidth
must also grow exponentially to avoid
limiting the performance scaling of
these systems. By increasing the data
per pin or cable of various electronic
devices and systems, such as memory,
graphics, chip-to-chip fabric, backplanes,
rack-to-rack designs, and local
area networks, wireline input-output
(IO) has fueled incredible technological
innovation in electronic devices
and systems. Figure 10 shows that the
data rate per pin has approximately
doubled every four years across various
IO standards, ranging from double
data rates (DDRs) to graphics and
high-speed Ethernet.
Figure 11 demonstrates that data
2022 2021
2020 2019
2018 2017
2016 2015
160
170
180
FoM (dB)
FIGURE 9: The SIR and IRR versus the FoM [FoM = -Sensitivity + 10 × log(data rate [b/s])
-10 × log(power [W])], as reported by ULP Rxs published at ISSCC.
256
128
64
32
16
8
4
2
1
0.5
0.25
2000 2004 2008 2012 2016 2020 2024
Year
FIGURE 10: The per-lane data rate versus the year for a variety of common IO standards.
DDR: double data rate; HDMI: High-Definition Multimedia Interface.
60 WINTER 2022
IEEE SOLID-STATE CIRCUITS MAGAZINE
190
200
210
PCIe
QPI/KTI
HT
SATA
SAS
USB
DDR
GDDR
CEI
Fiber
Channel
HDMI
DP
rates for published Txs have kept pace
with these standards while taking advantage
of CMOS scaling. Figure 12
describes the published Tx power efficiency
versus the channel losses at
the Nyquist frequency in the 40-50-dB
range. In part, this incredible improvement
is enabled by the power-performance
benefits of process technology
scaling. However, sustaining this exponential
trend for IO bandwidth requires
more than just transistor
scaling. Significant advances in energy
efficiency, channel equalization,
and clocking must be made to enable
the next generation of low-power and
high-performance computing (HPC)
systems. Papers at ISSCC this year include
an example of a pulse-amplitude
modulation (PAM)-4 Rx at >200 Gb/s;
PAM-4, long-reach, copper interconnect
Txs operating up to 112 Gb/s;
PAM-4, medium-reach electrical interconnects
operating up to 112 Gb/s;
PAM-4 electrical transmissions operating
up to >60 Gb/s over a high-loss
channel; a short-reach, optical, coherent
Rx operating up to 200 Gb/s; a
PAM-4 optical transmitter operating
up to 100 Gb/s; and a PAM-4 bidirectional
link operating up to 50 Gb/s on a
plastic waveguide. New techniques for
extending the data rate, power reduction,
channel equalization, and clock
recovery are reported. These Txs and
Per-Lane Transfer Rate (Gb/s)
SIR or IRR (dB)
IEEE Solid-States Circuits Magazine - Winter 2022

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